mmCP_RB_WPTR_POLL_CNTL 2216 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h #define mmCP_RB_WPTR_POLL_CNTL                                                                         0x0f62
mmCP_RB_WPTR_POLL_CNTL  212 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h #define mmCP_RB_WPTR_POLL_CNTL                                                                         0x01c2
mmCP_RB_WPTR_POLL_CNTL  212 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h #define mmCP_RB_WPTR_POLL_CNTL                                                                         0x01c2
mmCP_RB_WPTR_POLL_CNTL  206 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h #define mmCP_RB_WPTR_POLL_CNTL                                                                         0x01c2
mmCP_RB_WPTR_POLL_CNTL  524 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_6_0_d.h #define mmCP_RB_WPTR_POLL_CNTL 0x21C2
mmCP_RB_WPTR_POLL_CNTL  513 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_0_d.h #define mmCP_RB_WPTR_POLL_CNTL                                                  0x21c2
mmCP_RB_WPTR_POLL_CNTL  526 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_d.h #define mmCP_RB_WPTR_POLL_CNTL                                                  0x21c2
mmCP_RB_WPTR_POLL_CNTL  579 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_d.h #define mmCP_RB_WPTR_POLL_CNTL                                                  0x21c2
mmCP_RB_WPTR_POLL_CNTL  579 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_d.h #define mmCP_RB_WPTR_POLL_CNTL                                                  0x21c2