mmCP_RB1_WPTR_HI 4768 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h #define mmCP_RB1_WPTR_HI                                                                               0x1df7
mmCP_RB1_WPTR_HI 2403 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h #define mmCP_RB1_WPTR_HI                                                                               0x1057
mmCP_RB1_WPTR_HI 2702 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h #define mmCP_RB1_WPTR_HI                                                                               0x1057
mmCP_RB1_WPTR_HI 2640 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h #define mmCP_RB1_WPTR_HI                                                                               0x1057