mmCP_RB0_WPTR_HI_BASE_IDX 4763 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h #define mmCP_RB0_WPTR_HI_BASE_IDX                                                                      0
mmCP_RB0_WPTR_HI_BASE_IDX 2398 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h #define mmCP_RB0_WPTR_HI_BASE_IDX                                                                      0
mmCP_RB0_WPTR_HI_BASE_IDX 2697 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h #define mmCP_RB0_WPTR_HI_BASE_IDX                                                                      0
mmCP_RB0_WPTR_HI_BASE_IDX 2635 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h #define mmCP_RB0_WPTR_HI_BASE_IDX                                                                      0