mmCP_RB0_CNTL_BASE_IDX 4709 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h #define mmCP_RB0_CNTL_BASE_IDX                                                                         0
mmCP_RB0_CNTL_BASE_IDX 2340 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h #define mmCP_RB0_CNTL_BASE_IDX                                                                         0
mmCP_RB0_CNTL_BASE_IDX 2639 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h #define mmCP_RB0_CNTL_BASE_IDX                                                                         0
mmCP_RB0_CNTL_BASE_IDX 2577 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h #define mmCP_RB0_CNTL_BASE_IDX                                                                         0