mmCP_QUEUE_THRESHOLDS_BASE_IDX 2225 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h #define mmCP_QUEUE_THRESHOLDS_BASE_IDX                                                                 0
mmCP_QUEUE_THRESHOLDS_BASE_IDX  221 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h #define mmCP_QUEUE_THRESHOLDS_BASE_IDX                                                                 0
mmCP_QUEUE_THRESHOLDS_BASE_IDX  221 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h #define mmCP_QUEUE_THRESHOLDS_BASE_IDX                                                                 0
mmCP_QUEUE_THRESHOLDS_BASE_IDX  215 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h #define mmCP_QUEUE_THRESHOLDS_BASE_IDX                                                                 0