mmCP_PWR_CNTL_BASE_IDX 4817 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h #define mmCP_PWR_CNTL_BASE_IDX                                                                         0
mmCP_PWR_CNTL_BASE_IDX 2454 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h #define mmCP_PWR_CNTL_BASE_IDX                                                                         0
mmCP_PWR_CNTL_BASE_IDX 2753 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h #define mmCP_PWR_CNTL_BASE_IDX                                                                         0
mmCP_PWR_CNTL_BASE_IDX 2691 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h #define mmCP_PWR_CNTL_BASE_IDX                                                                         0