mmCP_PQ_WPTR_POLL_CNTL1_BASE_IDX 4835 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h #define mmCP_PQ_WPTR_POLL_CNTL1_BASE_IDX                                                               0
mmCP_PQ_WPTR_POLL_CNTL1_BASE_IDX 2473 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h #define mmCP_PQ_WPTR_POLL_CNTL1_BASE_IDX                                                               0
mmCP_PQ_WPTR_POLL_CNTL1_BASE_IDX 2769 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h #define mmCP_PQ_WPTR_POLL_CNTL1_BASE_IDX                                                               0
mmCP_PQ_WPTR_POLL_CNTL1_BASE_IDX 2705 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h #define mmCP_PQ_WPTR_POLL_CNTL1_BASE_IDX                                                               0