mmCP_PQ_WPTR_POLL_CNTL1 4834 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h #define mmCP_PQ_WPTR_POLL_CNTL1                                                                        0x1e24
mmCP_PQ_WPTR_POLL_CNTL1 2472 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h #define mmCP_PQ_WPTR_POLL_CNTL1                                                                        0x1084
mmCP_PQ_WPTR_POLL_CNTL1 2768 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h #define mmCP_PQ_WPTR_POLL_CNTL1                                                                        0x1084
mmCP_PQ_WPTR_POLL_CNTL1 2704 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h #define mmCP_PQ_WPTR_POLL_CNTL1                                                                        0x1084
mmCP_PQ_WPTR_POLL_CNTL1  263 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_0_d.h #define mmCP_PQ_WPTR_POLL_CNTL1                                                 0x3084
mmCP_PQ_WPTR_POLL_CNTL1  265 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_d.h #define mmCP_PQ_WPTR_POLL_CNTL1                                                 0x3084
mmCP_PQ_WPTR_POLL_CNTL1  296 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_d.h #define mmCP_PQ_WPTR_POLL_CNTL1                                                 0x3084
mmCP_PQ_WPTR_POLL_CNTL1  296 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_d.h #define mmCP_PQ_WPTR_POLL_CNTL1                                                 0x3084