mmCP_PQ_WPTR_POLL_CNTL 4832 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h #define mmCP_PQ_WPTR_POLL_CNTL                                                                         0x1e23
mmCP_PQ_WPTR_POLL_CNTL 2470 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h #define mmCP_PQ_WPTR_POLL_CNTL                                                                         0x1083
mmCP_PQ_WPTR_POLL_CNTL 2766 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h #define mmCP_PQ_WPTR_POLL_CNTL                                                                         0x1083
mmCP_PQ_WPTR_POLL_CNTL 2702 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h #define mmCP_PQ_WPTR_POLL_CNTL                                                                         0x1083
mmCP_PQ_WPTR_POLL_CNTL  262 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_0_d.h #define mmCP_PQ_WPTR_POLL_CNTL                                                  0x3083
mmCP_PQ_WPTR_POLL_CNTL  264 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_d.h #define mmCP_PQ_WPTR_POLL_CNTL                                                  0x3083
mmCP_PQ_WPTR_POLL_CNTL  295 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_d.h #define mmCP_PQ_WPTR_POLL_CNTL                                                  0x3083
mmCP_PQ_WPTR_POLL_CNTL  295 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_d.h #define mmCP_PQ_WPTR_POLL_CNTL                                                  0x3083