mmCP_PA_CINVOC_COUNT_LO_BASE_IDX 7071 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h #define mmCP_PA_CINVOC_COUNT_LO_BASE_IDX                                                               1
mmCP_PA_CINVOC_COUNT_LO_BASE_IDX 4589 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h #define mmCP_PA_CINVOC_COUNT_LO_BASE_IDX                                                               1
mmCP_PA_CINVOC_COUNT_LO_BASE_IDX 4841 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h #define mmCP_PA_CINVOC_COUNT_LO_BASE_IDX                                                               1
mmCP_PA_CINVOC_COUNT_LO_BASE_IDX 4797 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h #define mmCP_PA_CINVOC_COUNT_LO_BASE_IDX                                                               1