mmCP_PA_CINVOC_COUNT_HI_BASE_IDX 7073 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h #define mmCP_PA_CINVOC_COUNT_HI_BASE_IDX                                                               1
mmCP_PA_CINVOC_COUNT_HI_BASE_IDX 4591 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h #define mmCP_PA_CINVOC_COUNT_HI_BASE_IDX                                                               1
mmCP_PA_CINVOC_COUNT_HI_BASE_IDX 4843 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h #define mmCP_PA_CINVOC_COUNT_HI_BASE_IDX                                                               1
mmCP_PA_CINVOC_COUNT_HI_BASE_IDX 4799 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h #define mmCP_PA_CINVOC_COUNT_HI_BASE_IDX                                                               1