mmCP_NUM_PRIM_WRITTEN_COUNT3_LO_BASE_IDX 7031 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h #define mmCP_NUM_PRIM_WRITTEN_COUNT3_LO_BASE_IDX                                                       1
mmCP_NUM_PRIM_WRITTEN_COUNT3_LO_BASE_IDX 4549 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h #define mmCP_NUM_PRIM_WRITTEN_COUNT3_LO_BASE_IDX                                                       1
mmCP_NUM_PRIM_WRITTEN_COUNT3_LO_BASE_IDX 4801 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h #define mmCP_NUM_PRIM_WRITTEN_COUNT3_LO_BASE_IDX                                                       1
mmCP_NUM_PRIM_WRITTEN_COUNT3_LO_BASE_IDX 4757 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h #define mmCP_NUM_PRIM_WRITTEN_COUNT3_LO_BASE_IDX                                                       1