mmCP_NUM_PRIM_NEEDED_COUNT3_HI_BASE_IDX 7037 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h #define mmCP_NUM_PRIM_NEEDED_COUNT3_HI_BASE_IDX                                                        1
mmCP_NUM_PRIM_NEEDED_COUNT3_HI_BASE_IDX 4555 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h #define mmCP_NUM_PRIM_NEEDED_COUNT3_HI_BASE_IDX                                                        1
mmCP_NUM_PRIM_NEEDED_COUNT3_HI_BASE_IDX 4807 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h #define mmCP_NUM_PRIM_NEEDED_COUNT3_HI_BASE_IDX                                                        1
mmCP_NUM_PRIM_NEEDED_COUNT3_HI_BASE_IDX 4763 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h #define mmCP_NUM_PRIM_NEEDED_COUNT3_HI_BASE_IDX                                                        1