mmCP_MEM_SLP_CNTL_BASE_IDX 4819 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h #define mmCP_MEM_SLP_CNTL_BASE_IDX                                                                     0
mmCP_MEM_SLP_CNTL_BASE_IDX 2456 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h #define mmCP_MEM_SLP_CNTL_BASE_IDX                                                                     0
mmCP_MEM_SLP_CNTL_BASE_IDX 2755 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h #define mmCP_MEM_SLP_CNTL_BASE_IDX                                                                     0
mmCP_MEM_SLP_CNTL_BASE_IDX 2693 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h #define mmCP_MEM_SLP_CNTL_BASE_IDX                                                                     0