mmCP_MEC2_PRGRM_CNTR_START_BASE_IDX 4901 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h #define mmCP_MEC2_PRGRM_CNTR_START_BASE_IDX                                                            0
mmCP_MEC2_PRGRM_CNTR_START_BASE_IDX 2541 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h #define mmCP_MEC2_PRGRM_CNTR_START_BASE_IDX                                                            0
mmCP_MEC2_PRGRM_CNTR_START_BASE_IDX 2833 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h #define mmCP_MEC2_PRGRM_CNTR_START_BASE_IDX                                                            0
mmCP_MEC2_PRGRM_CNTR_START_BASE_IDX 2767 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h #define mmCP_MEC2_PRGRM_CNTR_START_BASE_IDX                                                            0