mmCP_MEC1_PRGRM_CNTR_START_BASE_IDX 4899 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h #define mmCP_MEC1_PRGRM_CNTR_START_BASE_IDX                                                            0
mmCP_MEC1_PRGRM_CNTR_START_BASE_IDX 2539 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h #define mmCP_MEC1_PRGRM_CNTR_START_BASE_IDX                                                            0
mmCP_MEC1_PRGRM_CNTR_START_BASE_IDX 2831 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h #define mmCP_MEC1_PRGRM_CNTR_START_BASE_IDX                                                            0
mmCP_MEC1_PRGRM_CNTR_START_BASE_IDX 2765 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h #define mmCP_MEC1_PRGRM_CNTR_START_BASE_IDX                                                            0