mmCP_MEC1_INTR_ROUTINE_START_BASE_IDX 4909 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h #define mmCP_MEC1_INTR_ROUTINE_START_BASE_IDX                                                          0
mmCP_MEC1_INTR_ROUTINE_START_BASE_IDX 2549 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h #define mmCP_MEC1_INTR_ROUTINE_START_BASE_IDX                                                          0
mmCP_MEC1_INTR_ROUTINE_START_BASE_IDX 2841 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h #define mmCP_MEC1_INTR_ROUTINE_START_BASE_IDX                                                          0
mmCP_MEC1_INTR_ROUTINE_START_BASE_IDX 2775 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h #define mmCP_MEC1_INTR_ROUTINE_START_BASE_IDX                                                          0