mmCP_ME0_PIPE0_PRIORITY_BASE_IDX 4739 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h #define mmCP_ME0_PIPE0_PRIORITY_BASE_IDX                                                               0
mmCP_ME0_PIPE0_PRIORITY_BASE_IDX 2374 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h #define mmCP_ME0_PIPE0_PRIORITY_BASE_IDX                                                               0
mmCP_ME0_PIPE0_PRIORITY_BASE_IDX 2673 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h #define mmCP_ME0_PIPE0_PRIORITY_BASE_IDX                                                               0
mmCP_ME0_PIPE0_PRIORITY_BASE_IDX 2611 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h #define mmCP_ME0_PIPE0_PRIORITY_BASE_IDX                                                               0