mmCP_INT_STATUS_RING1_BASE_IDX 4813 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h #define mmCP_INT_STATUS_RING1_BASE_IDX                                                                 0
mmCP_INT_STATUS_RING1_BASE_IDX 2450 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h #define mmCP_INT_STATUS_RING1_BASE_IDX                                                                 0
mmCP_INT_STATUS_RING1_BASE_IDX 2749 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h #define mmCP_INT_STATUS_RING1_BASE_IDX                                                                 0
mmCP_INT_STATUS_RING1_BASE_IDX 2687 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h #define mmCP_INT_STATUS_RING1_BASE_IDX                                                                 0