mmCP_INT_CNTL_RING1 4806 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h #define mmCP_INT_CNTL_RING1                                                                            0x1e0b
mmCP_INT_CNTL_RING1 2443 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h #define mmCP_INT_CNTL_RING1                                                                            0x106b
mmCP_INT_CNTL_RING1 2742 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h #define mmCP_INT_CNTL_RING1                                                                            0x106b
mmCP_INT_CNTL_RING1 2680 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h #define mmCP_INT_CNTL_RING1                                                                            0x106b
mmCP_INT_CNTL_RING1  439 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_6_0_d.h #define mmCP_INT_CNTL_RING1 0x306B
mmCP_INT_CNTL_RING1  223 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_0_d.h #define mmCP_INT_CNTL_RING1                                                     0x306b
mmCP_INT_CNTL_RING1  223 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_d.h #define mmCP_INT_CNTL_RING1                                                     0x306b
mmCP_INT_CNTL_RING1  247 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_d.h #define mmCP_INT_CNTL_RING1                                                     0x306b
mmCP_INT_CNTL_RING1  248 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_d.h #define mmCP_INT_CNTL_RING1                                                     0x306b