mmCP_INT_CNTL_RING0 4804 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h #define mmCP_INT_CNTL_RING0                                                                            0x1e0a
mmCP_INT_CNTL_RING0 2441 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h #define mmCP_INT_CNTL_RING0                                                                            0x106a
mmCP_INT_CNTL_RING0 2740 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h #define mmCP_INT_CNTL_RING0                                                                            0x106a
mmCP_INT_CNTL_RING0 2678 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h #define mmCP_INT_CNTL_RING0                                                                            0x106a
mmCP_INT_CNTL_RING0  438 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_6_0_d.h #define mmCP_INT_CNTL_RING0 0x306A
mmCP_INT_CNTL_RING0  222 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_0_d.h #define mmCP_INT_CNTL_RING0                                                     0x306a
mmCP_INT_CNTL_RING0  222 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_d.h #define mmCP_INT_CNTL_RING0                                                     0x306a
mmCP_INT_CNTL_RING0  246 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_d.h #define mmCP_INT_CNTL_RING0                                                     0x306a
mmCP_INT_CNTL_RING0  247 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_d.h #define mmCP_INT_CNTL_RING0                                                     0x306a