mmCP_INT_CNTL    4728 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h #define mmCP_INT_CNTL                                                                                  0x1de9
mmCP_INT_CNTL    2363 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h #define mmCP_INT_CNTL                                                                                  0x1049
mmCP_INT_CNTL    2662 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h #define mmCP_INT_CNTL                                                                                  0x1049
mmCP_INT_CNTL    2600 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h #define mmCP_INT_CNTL                                                                                  0x1049
mmCP_INT_CNTL     437 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_6_0_d.h #define mmCP_INT_CNTL 0x3049
mmCP_INT_CNTL     221 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_0_d.h #define mmCP_INT_CNTL                                                           0x3049
mmCP_INT_CNTL     221 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_d.h #define mmCP_INT_CNTL                                                           0x3049
mmCP_INT_CNTL     245 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_d.h #define mmCP_INT_CNTL                                                           0x3049
mmCP_INT_CNTL     246 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_d.h #define mmCP_INT_CNTL                                                           0x3049