mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI 5304 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h #define mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI                                                                0x1fb5
mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI 2816 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h #define mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI                                                                0x1251
mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI 3066 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h #define mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI                                                                0x1251
mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI 3022 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h #define mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI                                                                0x1251
mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI  579 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_0_d.h #define mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI                                         0x3251
mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI  592 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_d.h #define mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI                                         0x3251
mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI  642 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_d.h #define mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI                                         0x3251
mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI  642 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_d.h #define mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI                                         0x3251