mmCP_HQD_PQ_RPTR_REPORT_ADDR 5302 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h #define mmCP_HQD_PQ_RPTR_REPORT_ADDR                                                                   0x1fb4
mmCP_HQD_PQ_RPTR_REPORT_ADDR 2814 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h #define mmCP_HQD_PQ_RPTR_REPORT_ADDR                                                                   0x1250
mmCP_HQD_PQ_RPTR_REPORT_ADDR 3064 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h #define mmCP_HQD_PQ_RPTR_REPORT_ADDR                                                                   0x1250
mmCP_HQD_PQ_RPTR_REPORT_ADDR 3020 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h #define mmCP_HQD_PQ_RPTR_REPORT_ADDR                                                                   0x1250
mmCP_HQD_PQ_RPTR_REPORT_ADDR  578 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_0_d.h #define mmCP_HQD_PQ_RPTR_REPORT_ADDR                                            0x3250
mmCP_HQD_PQ_RPTR_REPORT_ADDR  591 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_d.h #define mmCP_HQD_PQ_RPTR_REPORT_ADDR                                            0x3250
mmCP_HQD_PQ_RPTR_REPORT_ADDR  641 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_d.h #define mmCP_HQD_PQ_RPTR_REPORT_ADDR                                            0x3250
mmCP_HQD_PQ_RPTR_REPORT_ADDR  641 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_d.h #define mmCP_HQD_PQ_RPTR_REPORT_ADDR                                            0x3250