mmCP_HQD_PQ_DOORBELL_CONTROL_BASE_IDX 5311 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h #define mmCP_HQD_PQ_DOORBELL_CONTROL_BASE_IDX                                                          0
mmCP_HQD_PQ_DOORBELL_CONTROL_BASE_IDX 2823 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h #define mmCP_HQD_PQ_DOORBELL_CONTROL_BASE_IDX                                                          0
mmCP_HQD_PQ_DOORBELL_CONTROL_BASE_IDX 3073 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h #define mmCP_HQD_PQ_DOORBELL_CONTROL_BASE_IDX                                                          0
mmCP_HQD_PQ_DOORBELL_CONTROL_BASE_IDX 3029 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h #define mmCP_HQD_PQ_DOORBELL_CONTROL_BASE_IDX                                                          0