mmCP_HQD_PQ_DOORBELL_CONTROL 5310 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h #define mmCP_HQD_PQ_DOORBELL_CONTROL 0x1fb8 mmCP_HQD_PQ_DOORBELL_CONTROL 2822 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h #define mmCP_HQD_PQ_DOORBELL_CONTROL 0x1254 mmCP_HQD_PQ_DOORBELL_CONTROL 3072 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h #define mmCP_HQD_PQ_DOORBELL_CONTROL 0x1254 mmCP_HQD_PQ_DOORBELL_CONTROL 3028 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h #define mmCP_HQD_PQ_DOORBELL_CONTROL 0x1254 mmCP_HQD_PQ_DOORBELL_CONTROL 582 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_0_d.h #define mmCP_HQD_PQ_DOORBELL_CONTROL 0x3254 mmCP_HQD_PQ_DOORBELL_CONTROL 595 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_d.h #define mmCP_HQD_PQ_DOORBELL_CONTROL 0x3254 mmCP_HQD_PQ_DOORBELL_CONTROL 645 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_d.h #define mmCP_HQD_PQ_DOORBELL_CONTROL 0x3254 mmCP_HQD_PQ_DOORBELL_CONTROL 645 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_d.h #define mmCP_HQD_PQ_DOORBELL_CONTROL 0x3254