mmCP_HQD_EOP_WPTR_MEM_BASE_IDX 5389 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h #define mmCP_HQD_EOP_WPTR_MEM_BASE_IDX                                                                 0
mmCP_HQD_EOP_WPTR_MEM_BASE_IDX 2901 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h #define mmCP_HQD_EOP_WPTR_MEM_BASE_IDX                                                                 0
mmCP_HQD_EOP_WPTR_MEM_BASE_IDX 3151 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h #define mmCP_HQD_EOP_WPTR_MEM_BASE_IDX                                                                 0
mmCP_HQD_EOP_WPTR_MEM_BASE_IDX 3107 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h #define mmCP_HQD_EOP_WPTR_MEM_BASE_IDX                                                                 0