mmCP_HPD_UTCL1_ERROR_BASE_IDX 5277 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h #define mmCP_HPD_UTCL1_ERROR_BASE_IDX                                                                  0
mmCP_HPD_UTCL1_ERROR_BASE_IDX 2789 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h #define mmCP_HPD_UTCL1_ERROR_BASE_IDX                                                                  0
mmCP_HPD_UTCL1_ERROR_BASE_IDX 3039 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h #define mmCP_HPD_UTCL1_ERROR_BASE_IDX                                                                  0
mmCP_HPD_UTCL1_ERROR_BASE_IDX 2995 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h #define mmCP_HPD_UTCL1_ERROR_BASE_IDX                                                                  0