mmCP_HPD_UTCL1_CNTL_BASE_IDX 5275 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h #define mmCP_HPD_UTCL1_CNTL_BASE_IDX                                                                   0
mmCP_HPD_UTCL1_CNTL_BASE_IDX 2787 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h #define mmCP_HPD_UTCL1_CNTL_BASE_IDX                                                                   0
mmCP_HPD_UTCL1_CNTL_BASE_IDX 3037 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h #define mmCP_HPD_UTCL1_CNTL_BASE_IDX                                                                   0
mmCP_HPD_UTCL1_CNTL_BASE_IDX 2993 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h #define mmCP_HPD_UTCL1_CNTL_BASE_IDX                                                                   0