mmCP_HPD_UTCL1_CNTL 5274 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h #define mmCP_HPD_UTCL1_CNTL                                                                            0x1fa6
mmCP_HPD_UTCL1_CNTL 2786 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h #define mmCP_HPD_UTCL1_CNTL                                                                            0x1242
mmCP_HPD_UTCL1_CNTL 3036 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h #define mmCP_HPD_UTCL1_CNTL                                                                            0x1242
mmCP_HPD_UTCL1_CNTL 2992 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h #define mmCP_HPD_UTCL1_CNTL                                                                            0x1242