mmCP_HPD_STATUS0_BASE_IDX 5273 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h #define mmCP_HPD_STATUS0_BASE_IDX                                                                      0
mmCP_HPD_STATUS0_BASE_IDX 2785 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h #define mmCP_HPD_STATUS0_BASE_IDX                                                                      0
mmCP_HPD_STATUS0_BASE_IDX 3035 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h #define mmCP_HPD_STATUS0_BASE_IDX                                                                      0
mmCP_HPD_STATUS0_BASE_IDX 2991 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h #define mmCP_HPD_STATUS0_BASE_IDX                                                                      0