mmCP_CPC_STALLED_STAT1_BASE_IDX 2129 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h #define mmCP_CPC_STALLED_STAT1_BASE_IDX                                                                0
mmCP_CPC_STALLED_STAT1_BASE_IDX  121 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h #define mmCP_CPC_STALLED_STAT1_BASE_IDX                                                                0
mmCP_CPC_STALLED_STAT1_BASE_IDX  121 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h #define mmCP_CPC_STALLED_STAT1_BASE_IDX                                                                0
mmCP_CPC_STALLED_STAT1_BASE_IDX  123 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h #define mmCP_CPC_STALLED_STAT1_BASE_IDX                                                                0