mmCP_CPC_IC_OP_CNTL_BASE_IDX 10263 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h #define mmCP_CPC_IC_OP_CNTL_BASE_IDX                                                                   1
mmCP_CPC_IC_OP_CNTL_BASE_IDX 2583 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h #define mmCP_CPC_IC_OP_CNTL_BASE_IDX                                                                   0
mmCP_CPC_IC_OP_CNTL_BASE_IDX 2875 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h #define mmCP_CPC_IC_OP_CNTL_BASE_IDX                                                                   0
mmCP_CPC_IC_OP_CNTL_BASE_IDX 2809 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h #define mmCP_CPC_IC_OP_CNTL_BASE_IDX                                                                   0