mmCP_CPC_IC_BASE_CNTL_BASE_IDX 10261 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h #define mmCP_CPC_IC_BASE_CNTL_BASE_IDX                                                                 1
mmCP_CPC_IC_BASE_CNTL_BASE_IDX 2581 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h #define mmCP_CPC_IC_BASE_CNTL_BASE_IDX                                                                 0
mmCP_CPC_IC_BASE_CNTL_BASE_IDX 2873 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h #define mmCP_CPC_IC_BASE_CNTL_BASE_IDX                                                                 0
mmCP_CPC_IC_BASE_CNTL_BASE_IDX 2807 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h #define mmCP_CPC_IC_BASE_CNTL_BASE_IDX                                                                 0