mmCP_CPC_IC_BASE_CNTL 10260 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h #define mmCP_CPC_IC_BASE_CNTL                                                                          0x584e
mmCP_CPC_IC_BASE_CNTL 2580 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h #define mmCP_CPC_IC_BASE_CNTL                                                                          0x10bb
mmCP_CPC_IC_BASE_CNTL 2872 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h #define mmCP_CPC_IC_BASE_CNTL                                                                          0x10bb
mmCP_CPC_IC_BASE_CNTL 2806 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h #define mmCP_CPC_IC_BASE_CNTL                                                                          0x10bb
mmCP_CPC_IC_BASE_CNTL  348 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_d.h #define mmCP_CPC_IC_BASE_CNTL                                                   0x30bb
mmCP_CPC_IC_BASE_CNTL  348 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_d.h #define mmCP_CPC_IC_BASE_CNTL                                                   0x30bb