mmCP_CPC_HALT_HYST_COUNT_BASE_IDX 2155 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h #define mmCP_CPC_HALT_HYST_COUNT_BASE_IDX                                                              0
mmCP_CPC_HALT_HYST_COUNT_BASE_IDX  143 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h #define mmCP_CPC_HALT_HYST_COUNT_BASE_IDX                                                              0
mmCP_CPC_HALT_HYST_COUNT_BASE_IDX  143 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h #define mmCP_CPC_HALT_HYST_COUNT_BASE_IDX                                                              0
mmCP_CPC_HALT_HYST_COUNT_BASE_IDX  145 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h #define mmCP_CPC_HALT_HYST_COUNT_BASE_IDX                                                              0