mmCPG_UTCL1_STATUS_BASE_IDX 5149 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h #define mmCPG_UTCL1_STATUS_BASE_IDX                                                                    0
mmCPG_UTCL1_STATUS_BASE_IDX 2639 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h #define mmCPG_UTCL1_STATUS_BASE_IDX                                                                    0
mmCPG_UTCL1_STATUS_BASE_IDX 2913 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h #define mmCPG_UTCL1_STATUS_BASE_IDX                                                                    0
mmCPG_UTCL1_STATUS_BASE_IDX 2847 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h #define mmCPG_UTCL1_STATUS_BASE_IDX                                                                    0