mmCPG_UTCL1_STATUS 5148 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h #define mmCPG_UTCL1_STATUS                                                                             0x1f54
mmCPG_UTCL1_STATUS 2638 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h #define mmCPG_UTCL1_STATUS                                                                             0x11b4
mmCPG_UTCL1_STATUS 2912 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h #define mmCPG_UTCL1_STATUS                                                                             0x11b4
mmCPG_UTCL1_STATUS 2846 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h #define mmCPG_UTCL1_STATUS                                                                             0x11b4