mmCPG_UTCL1_ERROR_BASE_IDX 4783 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h #define mmCPG_UTCL1_ERROR_BASE_IDX                                                                     0
mmCPG_UTCL1_ERROR_BASE_IDX 2418 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h #define mmCPG_UTCL1_ERROR_BASE_IDX                                                                     0
mmCPG_UTCL1_ERROR_BASE_IDX 2717 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h #define mmCPG_UTCL1_ERROR_BASE_IDX                                                                     0
mmCPG_UTCL1_ERROR_BASE_IDX 2655 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h #define mmCPG_UTCL1_ERROR_BASE_IDX                                                                     0