mmCPG_UTCL1_CNTL 4696 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h #define mmCPG_UTCL1_CNTL 0x1ddc mmCPG_UTCL1_CNTL 2327 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h #define mmCPG_UTCL1_CNTL 0x103c mmCPG_UTCL1_CNTL 2626 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h #define mmCPG_UTCL1_CNTL 0x103c mmCPG_UTCL1_CNTL 2564 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h #define mmCPG_UTCL1_CNTL 0x103c