mmCPF_UTCL1_STATUS_BASE_IDX 5153 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h #define mmCPF_UTCL1_STATUS_BASE_IDX                                                                    0
mmCPF_UTCL1_STATUS_BASE_IDX 2643 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h #define mmCPF_UTCL1_STATUS_BASE_IDX                                                                    0
mmCPF_UTCL1_STATUS_BASE_IDX 2917 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h #define mmCPF_UTCL1_STATUS_BASE_IDX                                                                    0
mmCPF_UTCL1_STATUS_BASE_IDX 2851 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h #define mmCPF_UTCL1_STATUS_BASE_IDX                                                                    0