mmCPC_UTCL1_STATUS_BASE_IDX 5151 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h #define mmCPC_UTCL1_STATUS_BASE_IDX                                                                    0
mmCPC_UTCL1_STATUS_BASE_IDX 2641 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h #define mmCPC_UTCL1_STATUS_BASE_IDX                                                                    0
mmCPC_UTCL1_STATUS_BASE_IDX 2915 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h #define mmCPC_UTCL1_STATUS_BASE_IDX                                                                    0
mmCPC_UTCL1_STATUS_BASE_IDX 2849 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h #define mmCPC_UTCL1_STATUS_BASE_IDX                                                                    0