mmCPC_UTCL1_STATUS 5150 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h #define mmCPC_UTCL1_STATUS                                                                             0x1f55
mmCPC_UTCL1_STATUS 2640 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h #define mmCPC_UTCL1_STATUS                                                                             0x11b5
mmCPC_UTCL1_STATUS 2914 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h #define mmCPC_UTCL1_STATUS                                                                             0x11b5
mmCPC_UTCL1_STATUS 2848 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h #define mmCPC_UTCL1_STATUS                                                                             0x11b5