mmCPC_UTCL1_CNTL_BASE_IDX 4699 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h #define mmCPC_UTCL1_CNTL_BASE_IDX                                                                      0
mmCPC_UTCL1_CNTL_BASE_IDX 2330 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h #define mmCPC_UTCL1_CNTL_BASE_IDX                                                                      0
mmCPC_UTCL1_CNTL_BASE_IDX 2629 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h #define mmCPC_UTCL1_CNTL_BASE_IDX                                                                      0
mmCPC_UTCL1_CNTL_BASE_IDX 2567 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h #define mmCPC_UTCL1_CNTL_BASE_IDX                                                                      0