mmCPC_UTCL1_CNTL 4698 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h #define mmCPC_UTCL1_CNTL                                                                               0x1ddd
mmCPC_UTCL1_CNTL 2329 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h #define mmCPC_UTCL1_CNTL                                                                               0x103d
mmCPC_UTCL1_CNTL 2628 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h #define mmCPC_UTCL1_CNTL                                                                               0x103d
mmCPC_UTCL1_CNTL 2566 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h #define mmCPC_UTCL1_CNTL                                                                               0x103d