mmCNVC_CUR1_CURSOR0_CONTROL_BASE_IDX 3975 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmCNVC_CUR1_CURSOR0_CONTROL_BASE_IDX                                                           2
mmCNVC_CUR1_CURSOR0_CONTROL_BASE_IDX 4863 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmCNVC_CUR1_CURSOR0_CONTROL_BASE_IDX                                                           2
mmCNVC_CUR1_CURSOR0_CONTROL_BASE_IDX 3925 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmCNVC_CUR1_CURSOR0_CONTROL_BASE_IDX                                                           2