mmCNVC_CFG1_FORMAT_CONTROL_BASE_IDX 3955 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmCNVC_CFG1_FORMAT_CONTROL_BASE_IDX                                                            2
mmCNVC_CFG1_FORMAT_CONTROL_BASE_IDX 4833 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmCNVC_CFG1_FORMAT_CONTROL_BASE_IDX                                                            2
mmCNVC_CFG1_FORMAT_CONTROL_BASE_IDX 3895 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmCNVC_CFG1_FORMAT_CONTROL_BASE_IDX                                                            2