mmCNVC_CFG1_FORMAT_CONTROL 3954 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmCNVC_CFG1_FORMAT_CONTROL                                                                     0x0d63
mmCNVC_CFG1_FORMAT_CONTROL 4832 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmCNVC_CFG1_FORMAT_CONTROL                                                                     0x0e3b
mmCNVC_CFG1_FORMAT_CONTROL 3894 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmCNVC_CFG1_FORMAT_CONTROL                                                                     0x0e3b