mmCNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX 3953 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmCNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX                                                 2
mmCNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX 4831 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmCNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX                                                 2
mmCNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX 3893 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmCNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX                                                 2