mmCM3_CM_MEM_PWR_CTRL_BASE_IDX 5329 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h #define mmCM3_CM_MEM_PWR_CTRL_BASE_IDX                                                                 2
mmCM3_CM_MEM_PWR_CTRL_BASE_IDX 6367 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h #define mmCM3_CM_MEM_PWR_CTRL_BASE_IDX                                                                 2
mmCM3_CM_MEM_PWR_CTRL_BASE_IDX 5429 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h #define mmCM3_CM_MEM_PWR_CTRL_BASE_IDX                                                                 2